Semiconductor packages typically involve one or more semiconductor dies integrated on a substrate, such as, a glass substrate. The substrate is then attached to a package base, such as, a printed circuit board (PCB). Passive components such as capacitors and inductors are usually formed on one side, such as, a bottom side, of the substrate. The substrate may be attached to the PCB, face down, such that the bottom side comprising the passive components is closest to the PCB. Ball grid arrays (BGAs) including solder balls may be utilized for forming the connections and attachment between the substrate and the PCB. Electrical connections between the PCB and the substrate may be formed with wire bonds and pads as known in the art.
For example, with reference to FIG. 1, a side view of a conventional semiconductor package 100 is illustrated. Package 100 includes glass substrate 102 with a passive component, inductor 104 attached on a bottom surface of glass substrate 102. The combination of glass substrate with inductor 104 is referred to as a two dimensional (2D) passive-on-glass (POG). The 2D POG comprising glass substrate 102 and inductor 104 is attached in a conventional face down configuration, as illustrated, to PCB 108 using solder balls which form BGA 106. In this configuration, an undesirably high inductance is formed between the inductor and PCB 108. Specifically, the separation 112 between inductor 104 and ground plane 110 of PCB 108 relates to significantly high inductance interference formed. Ground plane 110 is an electrically conductive surface connected to an electrical ground. For example, ground plane 110 may be a large area of copper foil which is connected to the ground terminal (not illustrated) of PCB 108, and serves as a ground or return path for current from the various components integrated on PCB 108.
To minimize the undesirable inductance interference and accompanying Q-factor degradation it is necessary to maintain separation 112 at as high a distance as possible. The conventional approaches for forming package 100 rely on BGA 106 to provide the necessary separation 112. However, BGA 106 is not well suited to meet such needs. It is difficult to achieve consistent and desired height among the various solder balls which form BGA 106. The solder balls also tend to be highly susceptible to reflow degradation. Furthermore, over the course of operation, the degeneration of the solder balls may lead to collapse of the 2D POG on PCB 108, due to high heat and stress which is common in semiconductor packages.
Even if the inductors and passive components are placed on the opposite side of the semiconductor substrate, in a flipped (or flip-chip or face-up) configuration (not illustrated, with inductor 104, for example, formed on the top side of glass substrate 102) wire bonds are conventionally utilized for forming electrical connections. Wire bonds introduce high resistance, particularly, as the complexity of the semiconductor dies increases. Wire bonds also tend to be expensive and unstable.
Accordingly, there is a need in the art for efficient and reliable integration of semiconductor packages, such as, 2D POG structures, which avoid the aforementioned problems.